1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor integrated circuit having a multilayer structure and a signal transmission method thereof.
2. Description of the Related Art
In general, packaging technology for semiconductor integrated circuits has features for miniaturization and mounting reliability. A stack package may have the features of high performance and small circuit size.
In the semiconductor industry, a “stack” means vertically stacking at least two or more semiconductor chips or packages. When a stack package is used in a semiconductor memory device, a memory capacity of the semiconductor memory device may be two or more times larger than a memory capacity of a semiconductor memory device that does not implement a stack package. Furthermore, the stack package not only increases the memory capacity, but it also more efficiently uses the mounting area. Also, the stack package has higher packaging density.
The stack package may be fabricated by the following methods. First, individual semiconductor chips may be stacked, and then packaged. Second, packaged individual semiconductor chips may be stacked. The individual semiconductor chips of the stacked semiconductor package are electrically coupled through metallic wires or by through silicon vias (TSVs). The stack package using TSVs has a structure where the physical and electrical coupling between semiconductor chips are vertically achieved by TSVs formed in the respective semiconductor chips. For reference, various methods are used to form the TSVs such as a via first process, a via last process, a via last from backside and so on.
FIGS. 1A to 1G illustrate a method for forming a TSV. In the following descriptions, a via middle process will be illustrated as an example. The via middle process forms a TSV in a state where a part of a circuit is formed in an active layer.
Referring to FIG. 1A, an active layer 104 and a transistor 106 are formed on a wafer substrate 102. Referring to FIG. 1B, the active layer 104 and the wafer substrate 102 are etched to form a groove with a designated depth, and the groove is filled with a conductive material, such as a metal (for example, copper), to provide the base of a TSV 108.
Referring to FIG. 1C, an interlayer dielectric layer 110 is formed on the active layer 104, and metal lines 112 are formed in the interlayer dielectric layer 110. The metal lines 112 are electrically coupled to the TSV 108 and the transistor 106. A TSV pad 114 is formed on the metal line above the TSV 108, and the TSV pad 114 will be used to electrically couple the TSV 108.
Referring to FIG. 1D, when the TSV pad 114 is formed, a bump 116 is formed and electrically coupled to the TSV pad 114. The bump 116 is a component that electrically couples the TSV 108 to a TSV formed in another semiconductor chip that is stacked. A carrier 118 is subsequently formed over the interlayer dielectric layer 110. The carrier 118 is a component that fixes a wafer during a wafer thinning process (shown in FIG. 1E), which is performed to expose one end of the TSV 108.
Referring to FIG. 1E, the wafer thinning process is performed to expose one of the ends of the TSV 108. A bump 120 is formed at the exposed end of the TSV 108, which was exposed by the wafer thinning process. Then, referring to FIG. 1F, the carrier 118 is removed. Accordingly, a semiconductor chip 100A for stacking is fabricated, and the bumps 116 and 120 are provided on the top and bottom of the semiconductor chip 100A.
Referring to FIG. 1G, the semiconductor chips 100A and 100B are stacked and the electrically coupled to each other through the bumps that are connected to the TSVs.
Hereafter, a signal transmission path through the plurality of vertically stacked semiconductor chips (hereafter, referred to as “semiconductor integrated circuit”) will be described.
FIG. 2 is a side view of a semiconductor integrated circuit illustrating how a signal applied to the semiconductor integrated circuit is transmitted to the respective semiconductor chips through TSVs. The respective semiconductor chips and the TSVs in the semiconductor integrated circuit of FIG. 2 may be illustrated similarly to FIGS. 1A to 1G. For illustration purposes, however, they are conceptually illustrated.
Referring to FIG. 2, a signal SIG is buffered into an internal signal SIG1 through a buffer BUF provided in a first semiconductor chip CHIP1, and transmitted to a TSV TSV1 while applied to the first semiconductor chip CHIP1. Furthermore, a signal SIG2 transmitted from the TSV TSV1 is transmitted to a TSV TSV2 while applied to a second semiconductor chip CHIP2. Furthermore, a signal SIG3 transmitted from the TSV TSV2 is transmitted to a TSV TSV3 while applied to a third semiconductor chip CHIP3. Furthermore, a signal SIG4 transmitted from the TSV TSV3 is applied to a fourth semiconductor chip CHIP4.
When the respective signals SIG, SIG1, SIG2, SIG3, and SIG4 are transmitted, a delay time caused by the buffer BUF provided in the first semiconductor chip CHIP1 may be represented by ‘tDbuf’, and a delay time caused by each of the TSVs TSV1, TSV2, and TSV3 may be represented by ‘tDtsv’. Referring to FIG. 3, the signal SIG1 applied to the first semiconductor chip CHIP1 is delayed by ‘tDbuf’ from the signal SIG, the signal SIG2 applied to the second semiconductor chip CHIP2 is delayed by ‘tDbuf+tDtsv’ from the signal SIG, the signal SIG3 applied to the third semiconductor chip CHIP3 is delayed by ‘tDbuf+(tDtsv*2)’ from the signal SIG, and the signal SIG4 applied to the fourth semiconductor chip CHIP4 is delayed by ‘tDbuf+(tDtsv*3)’ from the signal SIG. In short, the signals SIG1, SIG2, SIG3, and SIG4 are each increasingly delayed depending on the number of TSVs that the signal is transmitted through. Because of the delays caused by the TSVs TSV1, TSV2, and TSV3, skews may occur.
The signal delay as a result of the TSVs TSV1, TSV2, and TSV3 is caused by a parasitic resistor and a parasitic capacitor (R*C) formed by the TSVs TSV1, TSV2, and TSV3 and the bumps of the TSVs. The skews caused by the signal delay limits high-speed operation.